Główne pojęcia
This paper provides a survey of the work on quantum computing hardware for implementing cryptography algorithms for 7G networks, emphasizing the sources of imperfections that impact the overall system performance.
Streszczenie
The paper starts by presenting a quantum network optimization framework that includes implementation imperfections. To understand the sources of these imperfections, the paper surveys work on elementary components of the quantum system, such as qubit physics, quantum hardware building blocks, quantum computing gate libraries, and quantum memories.
The key highlights include:
- Modeling superconducting qubits, qubit gates based on spin states of coupled single-electron quantum dots, quantum logic using polarizing beam splitters, and quantum gates implemented by trapped ions.
- Discussing quantum computing gate libraries, including depth-optimal quantum circuits, exact minimization of quantum circuits, and decomposing continuous-variable operations into a universal gate library.
- Covering topics on integrated local unitaries, factorization of unitaries, and basis partitioning in quantum memories.
- Presenting several implementation examples of continuous-variable quantum key distribution, including discussions on imperfect channels, transceiver component modeling, protocols, and noise.
- Providing a network optimization framework that incorporates hardware imperfections to enable fair assessment of investments in hardware improvements versus system-level complexity.
Statystyki
The paper does not contain specific numerical data or metrics. It is a survey paper that provides a comprehensive overview of the relevant research in quantum computing hardware and its impact on network and computer applications.
Cytaty
The paper does not contain any direct quotes that are crucial to the key arguments.